1. Field of the Invention
The present disclosure generally relates to advanced FDSOI techniques and, more particularly, to the fabrication of capacitor structures in advanced FDSOI techniques.
2. Description of the Related Art
In the ongoing task to comply with constraints imposed by Moore's Law, FDSOI (“fully depleted silicon-on-isolator”) is currently favored as the basis for next generation technologies in the fabrication of semiconductor devices at technology nodes of 22 nm and beyond. Aside from FDSOI allowing the combination of high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques, fabrication processes as employed in FDSOI techniques are comparatively simple and actually represent a low risk evolution of conventional planar bulk CMOS techniques when compared to three-dimensional transistor designs, such as FinFETs.
In general, SOI techniques make use of a special kind of substrate being formed by a semiconductor layer, such as silicon, germanium or silicon germanium, formed on a buried oxide (BOX) layer, which is in turn formed on a semiconductor substrate. Conventionally, there are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI (fully depleted SOI) MOSFETs. For example, in an N-type PDSOI MOSFET, a P-type film is sandwiched between a gate oxide (GOX) and the BOX, where a thickness of the P-type film is such that the depletion region cannot cover the whole P-region. Therefore, to some extent, PDSOI devices may behave like bulk MOSFETs.
In FDSOI substrates, the thickness of the semiconductor layer is such that the depletion region covers the whole semiconductor layer. Herein, the GOX in FDSOI techniques supports fewer depletion charges than a bulk substrate and an increase in the inversion charges occurs in the fully depleted semiconductor layer, resulting in higher switching speeds.
In recent attempts to provide a simple way of meeting power/performance targets, back biasing was suggested for FDSOI devices. When adopting the concept of back biasing, a voltage is applied just under the BOX of target semiconductor devices. In doing so, the electrostatic control of the semiconductor device is changed and the threshold voltage is shifted to either obtain more drive current (hence, higher performance) at the expense of increased leakage current (forward back bias, FBB) or to cut leakage current at the expense of reduced performance. While back bias in planar FDSOI techniques is somewhat similar to body bias as implemented in bulk CMOS technologies, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. For example, back biasing can be utilized in a dynamic way on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue.
The effects of process and temperature variations may be reduced when back biasing techniques are employed. As a result, the design of circuits including such devices becomes much easier by greatly reducing the spread of performance that the designers have to address when designing a circuit. As back biasing further allows operation at consistently lower (and more constant) supply voltages, the power consumption of FDSOI devices is also reduced and electromigration and power density problems are eased.
The implementation of back bias in the setup of FDSOI techniques involves a local exposure of the bulk substrate, so-called BULEX (‘bulk exposed’) regions, that are to be contacted. Naturally, the bulk substrate has a height difference relative to an upper surface of the active semiconductor layer of an SOI substrate. Accordingly, a step height exists between BULEX regions and SOI substrates in the form of the BOX layer and the active semiconductor layer. In advanced technologies, the step height may be on the order of 30 nm, which raises big challenges in front end of line (FEOL) processing of advanced semiconductor devices. For example, the step height between the bulk semiconductor material (at the BULEX regions) and the upper surface of the active layer of an SOI substrate (at transistor devices) leads to uncontrollable variations in the critical dimensions, to large offsets between FDSOI and bulk structure critical dimensions and, particularly, in lithographical processes, to divots and crevices where film residues are hard to remove and which can cause shorts and leaks in the final circuit.
One conventional fabrication process for forming BULEX contacts besides SOI semiconductor devices will be explained with regard to FIGS. 1a-1d and 2a-2c below.
FIGS. 1a-1d schematically show, in a cross-sectional view, a known FEOL process for implementing a back bias contact via contacting a BULEX area beside an active region according to SOI techniques. With regard to FIG. 1a, a known SOI substrate region is schematically illustrated. As indicated above, an SOI substrate is formed by a base substrate material 101, on which a buried oxide (BOX) material 103, and an active silicon film 105 is provided.
Starting from the SOI substrate as schematically illustrated in FIG. 1a, a bulk exposed region 120 is formed adjacent to an SOI region 110 by techniques implemented for locally removing the BOX material 103 and the active silicon film 105, as shown in FIG. 1b. Herein, a mask pattern (not illustrated) may be formed via lithographical techniques, e.g., by forming a resist material (not illustrated) on a thin oxide liner 107 (passivation oxide) provided on the active silicon film 105 and lithographically patterning the resist material (not illustrated) such that a region, where the BULEX region 120 is to be provided, is not covered by the masking pattern (not illustrated). In removing the active silicon film 105 and the BOX material 103 in accordance with the masking pattern (not illustrated), a bulk exposed region 120 is locally formed.
Regarding FIG. 1c, a process of re-growing silicon material on the BULEX region 120 is preformed such that the step height between the BULEX region 120 and the active silicon film 105 in the SOI region 110 is reduced. However, as the height level of the re-grown silicon material 121 on the BULEX region 120 may not totally match the height level of the active silicon film 105, the re-grown silicon material 121 is overgrown and, as a consequence, a dislocation portion 123 is formed at the interface of the SOI region 110 and the BULEX region 120.
In order to avoid possible disadvantageous effects resulting from the dislocation 123, an STI region of sufficient width is formed at the interface by matching a trench 125 with a width dimension d1 into the SOI material and the re-grown silicon material 121 at the interface between the SOI region 110 and the BULEX region 120, as shown in FIG. 1d. Therefore, a separation between the BULEX region 120 and the SOI region 110 has to be implemented in order to remove the dislocation 123, therefore leading to an increased distance between a BULEX contact (not illustrated), which is to be formed on the BULEX region 120, relative to a semiconductor device (not illustrated), which is to be formed on and in the SOI region 110 during subsequent fabrication steps. Conventionally, a width of the trench 125 is greater than a width of normally formed STI trenches 126, i.e., d1>d2.
With regard to FIGS. 2a-2c, issues appearing with the step height difference between BULEX regions and SOI regions are illustrated. FIG. 2a schematically illustrates a semiconductor device structure at an early stage during fabrication, particularly before any gate structure is formed and an STI region 207 is provided within an SOI substrate structure (base substrate 201, BOX material 203 and active silicon film 205), where the STI structure 207 separates a first SOI region 210 and a second SOI region 220. The first SOI region 210 and the second SOI region 220 are herein covered by a thin oxide liner.
Subsequently, a BULEX region is formed in the second SOI region 220 by locally removing the BOX material 203 and the active silicon film 205 in the second SOI region 220. Accordingly, a step height h (see FIG. 2b) is provided between the BULEX region 220 and the SOI region 210. As the STI 207 is partially exposed when the BOX material 203 and the active silicon film 205 in the bulk exposed (BULEX) region 220 are removed, a step 230 is formed in the STI 207 resulting in a stepped STI structure 207′.
Subsequent to providing the BULEX region 220, a gate structure 211 is formed on the SOI region 210, as shown in FIG. 2c. The gate structure 211 is formed by depositing a gate dielectric material 215 and a gate electrode material 213 over the SOI region 210 and the BULEX region 220, forming a gate mask pattern (not illustrated) on the deposited materials and removing the deposited material in accordance with the gate mask pattern (not illustrated). After the gate stack 213, 215 is patterned, sidewall spacers 217 and the gate cap 219 are formed by depositing the spacer forming material and anisotropically etching the spacer forming material.
As a result of the gate stack patterning (herein, the anisotropic etching of the gate material) and the spacer forming process (herein, the anisotropic etching of the spacer forming material), residual material 232 of the gate stack and the spacer remains at the step 230 in the stepped STI structure 207′. The residual material 232 leads to a large BULEX-to-SOI distance and could possibly induce an undesired conducting structure at the stepped STI structure 207′.
In view of the above-described situation, it is desirable to provide a BULEX contact in FDSOI techniques without the issues as discussed above with regard to FIGS. 1a-2c. 
In addition to the scaling of active semiconductor devices, such as MOSFETs, other components, such as passive devices, e.g., capacitors, inductors, resistors and the like, are increasingly integrated into integrated circuits, thereby eliminating the need to incorporate separate discrete components in a circuit design that otherwise increases circuit size, power consumption and cost. Both the demands of smaller circuit design rules, and the desire to incorporate various passive components in an integrated circuit, however, has led to further challenges to overcome. For example, one type of passive component that is increasingly incorporated into many integrated circuit designs is a capacitor. A capacitor may be implemented as a metal-insulator-metal (MIM) capacitor which is typically formed from a stacked arrangement of materials that include top and bottom electrodes separated by an intermediate insulator layer incorporating a dielectric material in the outermost metal layers in an integrated circuit (e.g., between the fifth and sixth metallization layers), thus relatively far from the underlying semiconductor substrate such that parasitic capacitance effects with the substrate are minimized. On the other hand, MIM capacitors are usually fabricated in back-end-of-line (BEoL) processing and thus occupy large areas of integrated circuits.
Recently, silicon-insulator-silicon (SIS) capacitors are formed on SOI substrates in large scale integration. Upon scaling SIS capacitors, the capacity of SIS capacitors decreases and the tendency for leakage currents to occur increases. However, to provide a desired capacitance from a SIS capacitor within a smaller circuit area, an increase in the capacitance is actually required.
In view of the above situation, it is thus desirable to provide capacitor structures at advanced technology nodes with improved capacitance density.